This invention relates to a buffer circuit.
A buffer circuit which produces two output signals having opposite phases (hereinafter termed opposite output signals) in response to a single input signal is constructed to compare the input signal with a predetermined reference voltage signal for obtaining two opposite output signals and is important as a buffer element between an input circuit and an internal circuit in various electronic circuits. As the capacity of memory devices increases and as their operating speed increases, so an address buffer circuit for use with semiconductor memory devices becomes important. For this reason, in the following description, an address buffer circuit utilized in a semiconductor memory device is taken as a typical example.
An address buffer circuit is used in a semiconductor memory device for sending an address selection designation signal to a decoding circuit in accordance with an address input signal, and it is required in such an address buffer circuit that it accurately determine a designated address and operate at a high sensitivity and high speed, that its power consumption be small, that it includes a signal generating circuit, and that it can be designed readily and reduced in size for miniaturization of the chip.
Various circuits have been proposed which meet these requirements. FIG. 1 shows one example of the most advanced prior art circuit.
The circuit shown in FIG. 1 comprises a pre-circuit 11 essentially constituted by a flip-flop circuit which is made up of enhancement type field effect transistors (E-FET) Q.sub.31 and Q.sub.32 and which compares a single input signal A.sub.I with a predetermined reference voltage signal V.sub.REF to produce two opposite pre-output signals A'.sub.o and A'.sub.o, and a main circuit 12 essentially constituted by another flip-flop circuit made up of E-FETs Q.sub.41 and Q.sub.42 acting as a transfer gate which transfers the pre-output signals A'.sub.o and A'.sub.o according to a clock signal P.sub.11, and E-FETs Q.sub.47 and Q.sub.48 which produce two opposite output signals A.sub.o and A.sub.o when supplied with the pre-output signals A'.sub.o and A'.sub.o. One of the characteristic features of this circuit lies in that depletion type field effect transistors (D-FET) Q.sub.33 Q.sub.34, Q.sub.35 and Q.sub.36 are used in the pre-circuit. The operation of this circuit will be outlined as follows.
The operation of the pre-circuit will first be described. According to a clock signal .phi..sub.11, the input signal A.sub.I giving an address input and the reference voltage signal V.sub.REF are applied to nodes N.sub.13 and N.sub.14 via E-FETs (in the following merely designated as FET except D-FET) Q.sub.37 and Q.sub.38. While latching the applied signals by the clock signal .phi..sub.11, a clock signal .phi..sub.12 rises to raise the potential of these nodes N.sub.13 and N.sub.14 by the action of bootstrap capacitances C.sub.11 and C.sub.12. As a consequence, the conductivity of each of D-FETS Q.sub.35 and Q.sub.36 is caused to vary by the applied input signal A.sub.I and reference voltage signal V.sub.REF. Such a change is detected by the flip-flop circuit constituted by FETs Q.sub.31 and Q.sub.32 by making a clock signal .phi..sub.11 low level which appears at nodes N.sub.11 and N.sub.12 and is then sent out to the main circuit 12 as the pre-output signals A'.sub.o and A'.sub.o via FETs Q.sub.39 and Q.sub.40. If the clock signal .phi..sub.11 is still at a low level even after detection by the flip-flop circuit, the D-FETs Q.sub.33 and Q.sub.34 on the load side would be turned ON, thereby increasing power consumption. Accordingly, a one shot reverse phase signal as shown in FIG. 2 is used as the clock signal .phi..sub.11. Since the clock signal .phi..sub.11 is a one shot reverse phase signal, as the clock signal .phi..sub.11 rises again, the nodes N.sub.11 and N.sub.12 will be precharged through D-FETs Q.sub.33 and Q.sub.34 again, whereby their address determination information at the nodes N.sub.11 and N.sub.12 would be lost, and levels at the nodes N.sub.15 and N.sub.16 would be also lost. Thus, the FETs Q.sub.41 and Q.sub.42 are provided for the purpose of preventing such loss by separating the nodes N.sub.15 and N.sub.16 from the nodes N.sub.11 and N.sub.12 which are kept at high potential levels. The FETs Q.sub.41 and Q.sub.42 act as a transfer gate so that pre-output signals A'.sub.o and A'.sub.o are applied to nodes N.sub.15 and N.sub.16 in the main circuit 12 in accordance with a clock signal P.sub.11 and then detected by the flip-flop circuit comprising FETs Q.sub.47 and Q.sub.48. The detected signals are outputted as output signals A.sub.o and A.sub.o from output terminals 15 and 16. The circuit constituted by FETs Q.sub.43, Q.sub.45 and Q.sub.44 and Q.sub.46 is an output level ensuring circuit which produces an output having the same level as that of a clock signal .phi..sub.13 by bringing the potential levels of nodes N.sub.17 and N.sub.18 up to the levels above the level of the clock signal .phi..sub.13 by self-boost effect caused by gate-source capacitances of FETs Q.sub.45 and Q.sub. 46. The FETs Q.sub.49 and Q.sub.50 are provided for the purpose of preventing a low level floating in which a low level one of the pre-output signals A'.sub.o and A'.sub.o is maintained directly by a high level one of the output signals A.sub.o and A'.sub.o to turn ON one receiving such high level signal of FETs Q.sub.49 and Q.sub.50.
As described above, although this prior art circuit is advantageous in that its main circuit 12 is simple and compact in construction, it still involves the following problems. For example, the output information of the pre-circuit 11 which is transmitted to the nodes N.sub.15 and N.sub.16 is directly controlled by the output signals A.sub.o and A.sub.o through FETs Q.sub.49 and Q.sub.50. When the output signals A.sub.o and A.sub.o float, the outputs at the nodes N.sub.15 and N.sub.16 are lost. Consequently, as shown in FIG. 2, this circuit is inherently sensitive to mutual differences in timing between clock signals .phi..sub.11, P.sub.11 and .phi..sub.13. For example, should the clock signal P.sub.11 becomes a low level before the clock signal .phi..sub.11 becomes sufficiently low level, the main circuit would be disconnected from the pre-circuit before the address information is determined by the main circuit. This requires the clock signal generator to ensure correct timing. Such ensurance can be attained by increasing the time spacing (i.e. lowering frequency) but such expedient prevents high speed operations. Furthermore, as the clock signal .phi..sub.13 is required not only to directly maintain the output signal level, but also to drive a decoder circuit constituting the load of the address buffer circuit, it becomes necessary to provide a high power clock signal generating circuit having a high level of V.sub.DD. Such a circuit is complicated and uses large transistors, thereby preventing miniaturization of the chip.
Other prior art circuits also, require a clock signal that rises to the V.sub.DD source voltage level at the time of detection. In addition, there is the problem of time spacing described above. Accordingly, the requirement for clock signal generating circuit is severe, which makes it complex and difficult to design the circuit and prevents miniaturization of the circuit and high speed operation thereof.